forum.rcl-radio.ru — ATtiny45 timer1

Re: ATtiny45 timer1

2022-10-12T09:02:16Z

PWM TIMER1 PB4

void setup(){
DDRB |= (1 << PB4); 
PORTB |= (1 << PB4); 
cli();
 TCCR1 |= (1 << CTC1);   // CTC mode
 GTCCR |= (1 << PWM1B);
 GTCCR |= (1 << COM1B0);

 TCCR1 |= (1 << CS11)|(1 << CS10);// Prescaler 4
// 8000000/256/4= 7812,5 Hz
 OCR1B = 250; // 0...255 8bit
sei();
}

void loop(){}

Re: ATtiny45 timer1

2022-10-12T08:50:09Z

PWM TIMER1 PB1

void setup(){
DDRB |= (1 << PB1); 
PORTB |= (1 << PB1); 
cli();
 TCCR1 |= (1 << CTC1)|(1 << PWM1A);   // CTC mode
 TCCR1 |= (1 << COM1A0);

 TCCR1 |= (1 << CS11)|(1 << CS10);// Prescaler 4
// 8000000/256/4= 7812,5 Hz
 OCR1A = 180; // 0...255 8bit
sei();
}

void loop(){}

Re: ATtiny45 timer1

2022-10-12T07:02:10Z

МЕАНДР PB4

DDRB |= (1 << PB4); 
PORTB |= (1 << PB4); 
cli();
 TCCR1 |= (1 << CTC1);   // CTC mode
 GTCCR |= (1 << COM1B0);
 TCCR1 |= (1 << CS13)|(1 << CS12)|(1 << CS11)|(1 << CS10);// Prescaler 16384
// 8000000/(16384*(1+20))= 24,4140625
 OCR1C = 20; // 0...255 8bit
sei();
}

void loop(){}

Re: ATtiny45 timer1

2022-10-12T04:20:01Z

МЕАНДР PB1

void setup(){
DDRB |= (1 << PB1); 
PORTB |= (1 << PB1); 
cli();
 TCCR1 |= (1 << CTC1);   // CTC mode
 TCCR1 |= (1 << COM1A0);
 TCCR1 |= (1 << CS13)|(1 << CS12)|(1 << CS11)|(1 << CS10);// Prescaler 16384
// 8000000/(16384*(1+243))= 2,00115266
 OCR1C = 243; // 0...255 8bit
sei();
}

void loop(){}

Re: ATtiny45 timer1

2022-10-11T07:24:30Z

переполнение

void setup(){
DDRB |= (1 << PB0); 
PORTB |= (1 << PB0); 
cli();
TCCR1 |= (1 << CS12)|(1 << CS11)|(1 << CS10);// Prescaler 64
TIMSK |= (1 << TOIE1);
// 8000000/64/255 = 490,196078 Hz
sei();
}

void loop(){}

ISR(TIMER1_OVF_vect) { 
  PORTB ^= (1 << PB0);
}

ATtiny45 timer1

2022-10-11T04:22:55Z

CTC

void setup(){
DDRB |= (1 << PB0); 
PORTB |= (1 << PB0); 
cli();
OCR1A = 243; // 0...255 8bit
TCCR1 |= (1 << CTC1);   // CTC mode
TCCR1 |= (1 << CS13)|(1 << CS12)|(1 << CS11)|(1 << CS10);// Prescaler 16384
TIMSK |= (1 << OCIE1A);
// (8000000/((243+1)16384))=2,00115266 Hz
sei();
}

void loop(){}

ISR(TIM1_COMPA_vect) { 
  PORTB ^= (1 << PB0);
}